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Lattice Semiconductor
Table 2-1. TSMAC IP Core Input and Output Signals
Functional Description
Port Name
Type
Active State
Description
Data Out Enable . This signal is driven low whenever the TTSMAC IP
hdataout_en_n
Output
Low
core outputs valid data onto the hdataout bus. This signal can be used to
build a bi-directional data bus.
hdataout[7:0]
Output
N/A
Data Bus Output . The CPU reads the internal registers through the
data bus.
Transmit MAC Application Interface
tx_fifodata[7:0]
Input
N/A
Transmit FIFO Read Data Bus . The data from the FIFO is presented on
this bus.
Transmit FIFO Data Available . When asserted, this signal indicates
that the TxFIFO has data ready for transmission on the G/MII interface.
tx_fifoavail
Input
High
Once this signal is asserted by the client, a short delay later the frame
will be transmitted. The client needs to use an appropriate threshold on
the client FIFO to indicate that a frame is ready to be sent and use that
threshold as the tx_fifo_avail signal.
tx_fifoeof
Input
High
Transmit FIFO End of Frame . This signal is asserted along with the last
byte of frame data indicating the end of the frame.
Transmit FIFO Empty . This signal indicates that the TxFIFO is empty.
tx_fifoempty
Input
High
When this signal is asserted and the TSMAC IP core is reading the
FIFO, the under-run condition is transferred to the network through the
txer signal.
tx_sndpaustim[15:0]
Input
N/A
PAUSE Frame Timer . This signal indicates the PAUSE time value that
should be sent in the PAUSE frame.
PAUSE Frame Request . When asserted, the TSMAC IP core transmits
tx_sndpausreq
Input
High
a PAUSE frame. This is also the qualifying signal for the tx_sndpausetim
bus.
FIFO Control Frame . This signal indicates whether the current frame in
the Transmit FIFO is a control frame or a data frame. It is qualified by the
tx_fifoctrl
Input
N/A
tx_fifoavail signal. The following values apply:
? 1 = Control frame
? 0 = Normal frame
tx_staten
Output
High
Transmit Statistics Vector Enable . When asserted, the contents of the
statistics vector bus tx_statvec are valid.
Transmit FIFO Read . This is the TSMAC IP core Transmit FIFO read
request, asserted by the TSMAC IP core when it intends to read the cli-
ent FIFO. The MAC core will first assert the tx_macread signal if the cli-
tx_macread
Output
High
ent FIFO is not empty (i.e., tx_fifoempty = 0), after which the tx_macread
may de-assert (based on MAC processing) or re-assert (based on MAC
processing and if tx_fifoempty is still 0). The tx_macread signal should
be tied to the client FIFO read pin, and the FIFO empty pin should be
tied to the tx_fifoempty of the MAC core.
IPUG51_03.0, December 2010
15
Tri-Speed Ethernet MAC User’s Guide
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